The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a method for manufacturing a semiconductor package that can improve mounting reliability.
In general, a semiconductor package is manufactured by mounting a semiconductor chip to a substrate. In such a conventional package structure, electrical connection between the semiconductor chip and the substrate is mainly implemented through wire bonding.
However, in the conventional semiconductor package in which electrical connection is implemented through wire bonding, wires are likely to snap in a subsequent molding process, and limitations exist in reducing the thickness and size of the package due to the loops and lengths of the wires.
Also, since signal paths depend upon the lengths of the wires, it is difficult to secure electrical characteristics of the package. To alleviate this, a flip chip bonding technology of connecting a semiconductor chip and a substrate using bumps has been suggested.
According to the flip chip bonding technology, a semiconductor chip is mechanically attached to a substrate and is electrically connected with the electrodes of the substrate by bumps formed on the bonding pads of the semiconductor chip.
Accordingly, in the case of a package to which the flip chip bonding technology is applied, the occurrence of a fail due to snapping of a wire may be fundamentally solved.
Also, the thickness and the size of the package may be reduced, and in particular, a signal path length may be minimized, whereby the electrical characteristics of the package may be improved.
When manufacturing a semiconductor package using the flip chip bonding technology, studs or pillars are first formed on the bonding pads of the semiconductor chip using gold or copper, solders are formed directly on the bond fingers of the substrate or with separate studs formed, and the semiconductor chip and the substrate are aligned such that the bonding pads and the bond fingers are in one to one correspondence. Then, the two objects are joined with each other by applying, for example, pressure or heat.
Nevertheless, in the conventional art, because the separate studs should be formed on the bond fingers of the substrate, additional processes and additional costs are required.
Furthermore, in the conventional art, when the semiconductor chip and the substrate are aligned and joined with each other, poor junctions may result due to misalignment and unevenness between bumps caused by the warpage of the semiconductor chip. Accordingly, junction coupling force between the semiconductor chip and the substrate is likely to decrease.